This motherboard can support up to 2Gb of DDR266 RAM modules. Attached is part of the memory detail from the manual. If you need a copy of the manual. please click on this link to download :- ftp://serwery.optimus.pl/Servers/Motherboards/SE7501BR2/Dokumenty/se7501br2tps.pdf 3.1.2.2 Memory Configuration Memory interface between the MCH and DIMMs is 144 bits wide. This requires that two DIMMs be populated per bank in order for the system to operate. At least one bank has to be populated in order for the system to boot. If additional banks have less than two DIMMs, the memory for that bank(s) will not be available to the system. There are two banks of DIMMs, labeled Bank1 and Bank2. Bank1 contains DIMM locations DIMM1A and DIMM1B and Bank2 contains DIMM2A and DIMM2B. DIMM socket identifiers are marked with silk screen next to each DIMM socket on the baseboard. The sockets associated with any given bank are located next to each other. The baseboard's signal integrity is optimized when memory banks are populated in order. Therefore, DIMM Bank1 must be populated before Bank2. DIMM and memory configurations must adhere to the following: • DDR266 DDR registered DIMM modules • DIMM organization: x72 ECC • Pin count: 184 • DIMM capacity: 128 MB, 256 MB, 512 MB, 1 GB, 2 GB • Serial PD: JEDEC Rev 2.0 • Voltage options: 2.5 V (VDD/VDDQ) • Interface: SSTL2 • Two DIMMs must be populated in a bank for a 144-bit wide memory data path • One or two memory banks may be populated Table 2. Memory Bank Labels Memory DIMM Bank Row J8D22 (DIMM 1A), J8D15 (DIMM 1B) 1 0, 1 J8D7 (DIMM 2A), J8D1 (DIMM 2B) 2 2, 3 Note: Memory must be installed in pairs; DIMM Bank1 must be populated before DIMM Bank2. Memory within a DIMM bank must be identical; between banks only the DIMM size may be different. Functional Architecture Intel® Server Board SE7501BR2 Technical Product Specification 26 Revision 1.2 Intel Order Number C13977-003 Figure 3. Memory Bank Label Definition
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